This invention relates to integrated circuit packages and more particularly to integrated circuit packages having multiple semiconductor chips (dies).
A chip package is used to protect integrated circuit chips from contamination and abuse and is used to provide a durable and substantial electrical lead system for connecting integrated circuit chips onto an external printed circuit board or directly into a electronic product. There are numerous advantages to providing a multi-chip integrated circuit (IC) package over single-chip carriers. By placing multiple chips directly on a substrate that provides low-inductance and low-capacitance connections between the chips and the signal/power lines, and that supplies a very dense interconnection network, packaging density and system performance can be improved. The multi-chip package minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuities between the chips mounted on the substrate by replacing the die-wirebond-pin-board-pin-wirebond-die path with a much superior die-bump-interconnect-bump-die path. Additionally, narrower and shorter wires on the ceramic substrate have much less capacitance and inductance than the printed circuit board interconnections. It is often advantageous to stack multiple identical IC chips into the same chip package in order to increase memory without using valuable space on the printed circuit board.
With reference to FIG. 6, in the prior art, one of the common methods of combining IC chips into a single package is to use a stacked die IC package 50 in which the top IC chip 16 is smaller than the bottom IC chip 14 in order to allow access on the bottom IC chip 14 for wirebonding leads 26. If the two IC chips are the same size, as in the stacked IC die package 60 of FIG. 7, then the top IC chip 16 must be offset from the bottom IC chip 14 in order to allow wirebonding access to the bottom IC chip 14. This limits access for the wirebonding leads 26 to one or two sides of the package, which is frequently not practical for assembly. Another common method of combining IC chips of the same size, that is known in the prior art, involves placing one of the IC chips underneath the leadframe in a package, as shown in FIG. 8. In the IC package 70 of FIG. 8, the top IC chip 16 is stacked on top of the leadframe 18 of the chip package while the bottom IC chip 14 is attached underneath the leadframe 18. The disadvantage to the die-underneath method of FIG. 8 is that the chips must be mirror images of each other, thereby requiring two complete IC fabrication steps.
U.S. Pat. No. 5,399,898 to Rostoker discloses multi-chip, multi-tier semiconductor package arrangements based upon single and double-sided flip chips. These arrangements are based on a stacked structure similar to FIGS. 6 and 7 noted above. U.S. Pat. No. 5,656,553 to Leas et al. discloses a fabrication method and resultant monolithic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The stacked die arrangement shown in the ""553 patent uses edge connections to connect the upper die to the lower die. While this method of stacking multiple IC die addresses the case where two identical die are stacked, the method does not allow for routing flexibility, as the circuit routing is vertical from top to bottom and if there is any crossover, the chip package will not operate properly.
It is the object of the present invention to provide a multi-chip IC package having two or more similar semiconductor IC chips.
It is a further object of the invention to provide a multi-chip IC package having two or more similar IC chips that does not limit wirebonding to one side of the chip and does not require two complete IC fabrication steps.
It is still a further object of the invention to provide a multi-chip IC package that allows for flexibility in circuit routing.
The above objects have been met by a dual-die integrated circuit package having two chips (dies) which can be identically constructed from a wafer fabrication processing standpoint and are xe2x80x9cflip chipxe2x80x9d attached to each other using standard solder bumping and solder reflow technology. The first chip is aligned at a specified angle in relation to the second chip such that at least one of the bonding pads on the surface of each of the chips remain exposed for connection into a standard chip package. In one embodiment of the invention, two rectangular chips are aligned such that one chip is rotated at an angle of 90 degrees in relation to the other chip, such that the non-overlapping surfaces are exposed to enable chip package assembly. In another embodiment of the invention, the chips are aligned at an angle of less than 90 degrees such that at least a small portion, such as a corner, of each chip is exposed for chip package assembly. This embodiment would be preferable for the case when the two chips are of a square shape. In another embodiment of the invention, the two chips are of different sizes, as a larger chip is arranged on top of a smaller chip and is rotated at an angle such that the lower chip has at least some minimum area accessible for assembly. This ability to mount a larger IC chip over a smaller IC chip would be valuable to an IC manufacturer who controls the design of the smaller die, but purchases the larger die from another source.
The present invention allows for doubling the functionality or memory of a chip package while using the same package footprint as a single chip and using only one IC design. The integrated circuit package of the present invention allows for flexibility in wirebonding and routing and can be implemented in a single IC fabrication step. The present invention allows IC manufacturers to develop products with double the memory or functionality in a much faster time frame by providing the ability to use multiple identical chips in the same package without having to make significant design changes to the chips.